Integrated circuit devices may experience significant variations due to manufacturing imperfections. A large portion of these variations are found in all dice, and are therefore characterized as systematic variations. Any remaining variations are unpredictable and are therefore characterized as random variations. A conventional timing characterization of integrated circuit devices specifies resource delays such that a certain percentage of dice do not violate resource delay specifications. The percentage of devices that do not violate the resource delay specifications is known as a timing yield. Because conventional timing characterization methods do not account for the fact that certain resources of a device may be consistently faster, conventional speed characterization methods lead to pessimistic resource delay specifications.
It is common for large silicon dice to exhibit variations in the performance of logic elements and interconnect elements. These variations may be due to lithography, mask making, or some other process required in the manufacturing of the integrated circuit devices. Checking for variations between dice is generally done by the testing a large number of dice in order to identify and correct any variations. After all improvements to the process are made at the fabricator of the devices, any remaining variation must be taken into account by de-rating the dice, where timing data for the slowest elements are used to characterize the devices. However, such a characterization may be unduly pessimistic and may not accurately reflect the speed of the device.